Modeling State in Software Debugging of VHDL-RTL Designs -- A Model-Based Diagnosis Approach

摘要

In this paper we outline an approach of applying model-based diagnosis to thefield of automatic software debugging of hardware designs. We present ourvalue-level model for debugging VHDL-RTL designs and show how to localize theerroneous component responsible for an observed misbehavior. Furthermore, wediscuss an extension of our model that supports the debugging of sequentialcircuits, not only at a given point in time, but also allows for consideringthe temporal behavior of VHDL-RTL designs. The introduced model is capable ofhandling state inherently present in every sequential circuit. The principalapplicability of the new model is outlined briefly and we use industrial-sizedreal world examples from the ISCAS'85 benchmark suite to discuss thescalability of our approach.